1. Field of the Invention
The invention is directed generally to Insulated Gate Field Effect Transistors (IGFETs). The invention is more specifically directed to a method for predicting the amount of leakage current which will occur over time in IGFETs and systems fabricated with IGFET's as a result of a hot-carrier induced leakage mechanism. The invention is also more specifically directed to a method for designing high-density, low-power, IGFET-based integrated circuits so that the circuits will reliably meet life-time leakage specifications despite their tendency to leak more current as post-manufacture utilization time increases.
2. Cross Reference to Related Documents
The following documents are believed relevant to the below discussion and are incorporated herein by reference:
(A) Peng Fang et al., "A Method to Project Hot Carrier Induced Punchthrough Voltage Reduction for Deep Submicron LDD PMOS FETs at Room and Elevated Temperatures," International Reliability Physics Symposium, pp. 131-135, March 1992.
(B) Mitsumasa Koyanagi et al., "Hot-Electron Punchthrough (HEIP) Effect in Submicrometer PMOSFET's," IEEE Trans. Electron Devices, Vol. ED-34, No. 4, April 1987, pp 839-844.
3. Description of the Related Art
The phenomenon of punchthrough voltage reduction due to hot-carrier injection of charged particles into the gate oxide of IGFETs is known in the art. (See above cited IRPS paper by P. Fang et al.)
In brief, the phenomenon unfolds during post-manufacture utilization. When a field effect transistor (FET) is held in a turned-on state (conductive state), charge carriers move through a channel region of the transistor from a source region to a drain region. The moving charge carriers gain more and more energy as they come closer and closer to the drain region. Some of the highly-energized charge carriers that are approaching the drain region collide with nuclei of the channel region and generate electron-hole pairs or other ionized anomalies. Due to the distribution of electric fields near the drain, the electron and hole of each collision-induced electron-hole pair tend to separate from one another and preferentially migrate towards or away from the gate of the device. Some of the migrating charge-particles become trapped in the gate insulating layer that separates the gate from the channel or at the interface of the gate insulating layer and the channel.
When a turn-off voltage is later applied to the gate of the same transistor for the purpose of switching the transistor into an off state, it is expected that no current will flow through the device. However, the charged particles which have collected over time and become trapped at the channel/gate-insulator interface, or within the gate insulating layer, reduce the effective channel length. This in turn reduces the punchthrough voltage (V.sub.pt) of the device. Operation at or above the punchthrough level induces an undesirable flow of leakage current between the source and drain. Such leakage current, when it occurs due to operation at or slightly above the punchthrough level, is typically on the order of one or less microampere (.ltoreq.1 .mu.A) per transistor and is rarely thought to be of consequence when one considers a circuit having only a few transistors.
However, modern integrated circuit designs usually call for the inclusion of millions of transistors on a single monolithic substrate. A leakage current of just one nanoampere (1 nA) per transistor translates into a larger scale leakage current of one or more milliamperes (.ltoreq.1 mA) per integrated circuit (IC) chip in high-density designs that sport millions of transistors per IC chip. This magnitude of leakage is generally unacceptable in low-power environments. It is particularly unacceptable when the IC chip is one of many like-leaking devices, all residing in a system that is supposed to have very low power consumption.
An example of such a power-frugal system is a portable "notebook" or "palmtop" computer that is to be powered by a battery of limited amp/hours. It is common to require such a computer to have one or more power-conserving standby modes in which the power consumption of inactive computing resources is minimized by putting them to "sleep". This helps to extend the operating time of the computer after each battery charge. Mobile systems such as hand-carried, or in-vehicle cellular telephones constitute another example of systems are typically required to be power-frugal.
Circuit designers need to have a clear understanding of not only what the punchthrough voltage of each IGFET is, but also a quantitative appreciation of the total amount of leakage current that will be drawn by each IC chip in a low-power standby mode. They also need to have a clear understanding of how each design choice exacerbates or mitigates leakage over time so that they may intelligently produce a low-power design that remains so over a specified system lifetime.
System lifetimes are typically specified as being at least 1 year to 3 years in order to satisfy consumer warranty requirements, and more often as being at least 5 to 10 years, to satisfy market requirements. The required lifetime of a given system can, of course, be much longer. It is often required, or at least desirable, to keep the power consumption of circuits that are in low-power standby mode below a specified maximum during the specified lifetime of the system.
Unfortunately, IGFET's are subject to degradation mechanisms which can increase their off-state leakage current and thereby make it is difficult to guarantee low power consumption over a one year or longer lifetime. In particular, it is to be expected that hot-carrier-induced leakage will increase over time because more and more charged particles become trapped by the gate insulating layer as device utilization time accumulates and effective channel length decreases.
There has been little investigation to date of the quantitative interrelation between design parameters and the rate at which leakage current increases over time as a result of post-manufacture utilization. The integrated circuit industry has been rushing forward to designs of smaller and smaller channel lengths, and through this path, to designs of ever higher integration densities, with little regard to the kinds of leakage problems that may develop as channel lengths become smaller and smaller.
A sound methodology is needed for accurately predicting the amount of leakage that will be seen over the operational lifetime of a new system (which lifetime is usually specified as 5-10 years). This is particularly so in cases where a planned system is to employ millions of insulated gate field effect transistors (IGFET's) each having a channel length in the submicron (.ltoreq.1 .mu.m) or deep-submicron (.ltoreq.0.5 .mu.m) range.